The present invention relates to a semiconductor device. More particularly, the present invention relates to a high frequency equalizer using a demultiplexing technique and a related semiconductor device.
As the clock signal frequency of central processing units (CPUs) significantly increases, the bandwidth of memory devices required by a system must also increase. In order to increase the bandwidth of memory devices, the synchronous DRAM (SDRAM) has been developed.
In addition, as semiconductor device manufacturing processes become more advanced, system performance is restricted by the data transmission speed between semiconductor devices, for example, between the DRAM and the CPU, rather than by semiconductor device speed.
Therefore, the joint electronic device engineering council (JEDEC) standard for a stub series-terminated transceiver logic (SSTL) method has been provided for increasing the data transmission speed between a DRAM and a CPU. In the SSTL method, speed is increased by impedance matching a transmission line, i.e., a bus, in order to reduce reflected waves, which are generated when a conventional low voltage TTL (LVTTL) method is used. However, in the SSTL method, power consumption is increased by the existence of a resistance required for impedance matching. Also, it is difficult to perform data processing with a high speed CPU without experiencing a bottleneck phenomenon.
Therefore, a Rambus method, where the input and output circuits of the DRAM and a bus system are changed in order to increase data transmission speed between the DRAM and the CPU, has been recently provided. However, as the number of DRAMs connected to the bus increases in the Rambus method, the parasitic load of the bus similarly increases. Accordingly, the frequency bandwidth of the bus is restricted, thus restricting the transmission speed of the bus. Therefore, the high frequency component of the data transmitted through the bus is lost. In order to solve such a problem, a method of restoring the lost high frequency component of the data at a receiver has been provided.
FIG. 1 is a schematic block diagram of a conventional high frequency component restoring apparatus. FIG. 2 is a graph showing a signal transient response characteristic of a channel for describing the conventional high frequency restoring apparatus shown in FIG. 1.
Referring to FIG. 1, the conventional high frequency component restoring apparatus includes an input port 11, an output port 12, a plurality of delayers 13 through 16, a plurality of multipliers 17 through 20, an adder 21, and a voltage comparator 22. The input port 11 receives current input data Vin transmitted through a channel whose frequency bandwidth is restricted, i.e., a bus. The output port 12 outputs output data Din, which has its lost high frequency component restored. The delayers 13 through 16 retain the input data of a previous period of time. The multipliers 17 through 20 obtain fluctuation values caused by interference signals a1 through a4 of the input data of the previous period of time. The adder 21 subtracts these fluctuation values from the current input data Vin. And the voltage comparator 22 compares the output signal of the adder 21 with a predetermined value.
In operation, when a predetermined pulse signal IP is transmitted through a channel whose frequency bandwidth is restricted, and is input to the input port 11 as shown in FIG. 2, various responses are included in the current input data Vin input through the input port 11. In particular, when the level of the input data Vin is “1” after one period T (See FIG. 2), the influence of this “1” is continuously experienced. In other words, after a period 2T, an interference signal a1 is experienced; after 3T, an interference signal a2 is experienced; after 4T, an interference signal a3 is experienced; and after 5T, an interference signal a4 is experienced. Accordingly, the interference signals a1 through a4 affect the next input data. The high frequency component of the input data is lost, but it is possible to correctly determine the next input data and to restore the high frequency component after removing the influence of the interference signals.
Therefore, in the high frequency component restoring apparatus according to the conventional technology, the fluctuation values due to the interference signals a1 through a4 are obtained by retaining the input data of the previous period of time by using the delayers 13 through 16 and multiplying the input data of the previous period of time, i.e., the output signals of the delayers 13 through 16, by the interference signals a1 through a4 of the input data of the previous period of time using the multipliers 17 through 20. Then, the influence of the interference signals is removed by subtracting the fluctuation values caused by the interference signals a1 through a4 of the input data of the previous period of time, i.e., the output signals of the multipliers 17 through 20, from the current input data Vin using the adder 21. Accordingly, the lost high frequency component of the current input data Vin is restored and the restored input data Din is then output from the voltage comparator 22.
However, in the conventional apparatus and method for restoring high frequency component, the amount of time assigned to restore the high frequency component is equal to the period of the input data. Therefore, when the data transmission speed increases, thus reducing the period of the input data, the amount of time assigned to restore the high frequency component is also shortened. Unfortunately, the lost high frequency component cannot be correctly restored at a high transmission speed. Also, in the conventional apparatus and method for restoring the high frequency component, a demultiplexing method of arranging a plurality of circuits shown in FIG. 1 in parallel to process input data, for solving the above problem cannot be applied.